Electronic equipment such as microprocessors, graphics processors, network processors, digital signal processors, etc. must often respond very fast to large step-type load transients. Switching power converters preferably have a voltage response that follows the ideal target voltage closely while reducing ring back. A system with such a transient response often behaves well over a wide frequency range of load changes. Some conventional switching regulators typically employ either a very high number of current samples per cycle or one current sample per cycle to understand the current conditions at the output of the regulator. In the case of multiple current samples per cycle, high quality ADCs (analog-to-digital converters) are needed to acquire the sample which significantly increases the system cost, increases power consumption and requires more area on the chip. On the other hand, only a single current sample per cycle introduces a significant latency into the current loop and results in poor transient response of the switching regulator. Other conventional switching regulators provide adaptive voltage positioning (AVP) to minimize the voltage excursion during high frequency repetitive load changes, i.e. to minimize the output impedance. Typically the voltage is sampled at a high rate, but the inductor current is sampled at a much lower rate. At load changes, the AVP loop introduces a high latency into the control system and causes ring back and unfavorable voltage response or output impedance peaking because of the low inductor current sampling rate.